Download PDF by Vijay Degalahal, R. Ramanarayanan (auth.), Manfred Glesner,: VLSI-SOC: From Systems to Chips: IFIP TC 10/ WG 10.5 Twelfth
By Vijay Degalahal, R. Ramanarayanan (auth.), Manfred Glesner, Ricardo Reis, Leandro Indrusiak, Vincent Mooney, Hans Eveking (eds.)
International Federation for info Processing
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Additional info for VLSI-SOC: From Systems to Chips: IFIP TC 10/ WG 10.5 Twelfth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2003), December 1–3, 2003, Darmstadt, Germany
2006, in IFIP International Federation for Information Processing, Volume 200, VLSI-SOC: From Systems to Chips, eds. , (Boston: Springer), pp. 21-37. 22 1. Joao M. S. Silva, Luis Miguel Silveira Introduction Substrate behavior in integrated circuits has long ceased to be considered as a perfect insulator [Joardar, 1994; Kup et al, 1991; Gharpurey, 1995], As MOS process' transistor channel widths decrease to the size of a few nanometers, digital clock frequencies have been steadily increasing, so that current injection into the polysilicon substrate becomes a great concern.
In the static design phase (the SoC hardware design phase) a set of applications to be run on the target system is profiled by simulation. Based on the profiling information, a design constraint library and an existing component implementation library, a set of required execution components is determined (Mapping Step). In a second Placement Step the required IP components are placed on the hyper-platform and the NoC is customized, considering the communication closeness of the IP blocks. After manufacturing, a dynamic recon- i^iim^gin^i HW Library Dynamic Allocation/ReMapping during Operation iiiiiiiiiiiH O Q •—Ul—•—El ^ Figure 6.
Transform domain techniques for efficient extraction of substrate parasitics. In Proceedings of the Int. Conf. on Computer-Aided Design, pages 461-467. Joardar, Kuntal (1994). A simple approach to modeling cross-talk in integrated circuits. IEEE Journal of Solid-state Circuits, 29(10): 1212-1219. Johnson, T. , and Wang, W (1984). Chip substrate resistance modeling technique for integrated circuit design. IEEE Transactions on Computer-Aided Design of Integrated Circuits, CAD-3(2): 126-134. , and White, J.
VLSI-SOC: From Systems to Chips: IFIP TC 10/ WG 10.5 Twelfth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2003), December 1–3, 2003, Darmstadt, Germany by Vijay Degalahal, R. Ramanarayanan (auth.), Manfred Glesner, Ricardo Reis, Leandro Indrusiak, Vincent Mooney, Hans Eveking (eds.)